Programmable logic devices (“PLDs”) are a well-known type of integrated circuit that can be programmed to perform specified logic functions. One type of PLD, the field programmable gate array (“FPGA”), typically includes an array of programmable tiles. These programmable tiles can include, for example, input/output blocks (“IOBs”), configurable logic blocks (“CLBs”), dedicated random access memory blocks (“BRAMs”), multipliers, digital signal processing blocks (“DSPs”), processors, clock managers, delay lock loops (“DLLs”), and so forth. Notably, as used herein, “include” and “including” mean including without limitation.
One such FPGA is the Xilinx Virtex® FPGA available from Xilinx, Inc., 2100 Logic Drive, San Jose, Calif. 95124. Another type of PLD is the Complex Programmable Logic Device (“CPLD”). A CPLD includes two or more “function blocks” connected together and to input/output (“I/O”) resources by an interconnect switch matrix. Each function block of the CPLD includes a two-level AND/OR structure similar to those used in Programmable Logic Arrays (“PLAs”) and Programmable Array Logic (“PAL”) devices. Other PLDs are programmed by applying a processing layer, such as a metal layer, that programmably interconnects the various elements on the device. These PLDs are known as mask programmable devices. PLDs can also be implemented in other ways, for example, using fuse or antifuse technology. The terms “PLD” and “programmable logic device” include but are not limited to these exemplary devices, as well as encompassing devices that are only partially programmable.
For purposes of clarity, FPGAs are described below though other types of PLDs may be used. FPGAs may include one or more embedded microprocessors. For example, a microprocessor may be located in an area reserved for it, generally referred to as a “processor block.”
Linear filters, such as Finite Impulse Response (“FIR”) and Infinite Impulse Response (“IIR”) filters, have known limitations regarding effectively removing impulse-like noises while preserving the edges of an original image. Non-linear filters, such as rank order filters, in contrast may be effective for removing impulse-like noises while preserving the edges of an original image. Accordingly, use of rank order filters may be useful for image pre-processing before edge detection or removing impulse-like transmission noises.
A rank order filter conventionally orders contents of a filter kernel (“window”) and selects a sample indexed by rank. Conventionally, samples are rank ordered according to magnitude. A sample or pixel with a target rank may be selected for output. For example, the sample with a target rank may replace a center sample in such filter window in a filter output. Examples of ranks include median, minimum, and maximum, among other known examples of ranking. Thus, for these three specific examples, the median value, the minimum value, and the maximum value, respectively, would be selected in each of the different types of rank ordering for output from a rank order filter. Thus, it should be appreciated that sample size may affect image quality.
Accordingly, it would be desirable and useful to provide a scalable architecture for rank order filters extended to two-dimensional (“2D”) filters for image and video processing.